This invention relates generally to semiconductor manufacture, and more particularly to an improved method and system for fabricating solder bumps on semiconductor components, such as wafers, dice, and chip scale packages.
Various semiconductor components include solder bumps, rather than flat bond pads, to provide electrical access to the integrated circuits contained on the component. For example, semiconductor wafers, dice, and chip scale packages, can include solder bumps. The solder bumps allow the dice, or packages, to be flip chip mounted to a printed circuit board, or other supporting substrate.
Different fabrication processes have been developed by semiconductor manufacturers for forming the solder bumps. A typical wafer-level fabrication process utilizes solder wettable pads deposited on aluminum electrodes of the component. The wafer can include a passivation layer, such as BPSG glass, having openings on which the solder wettable pads are formed. Typically, the pads include an adherence layer, such as chromium, which provides adherence to the electrodes and passivation layer. The adherence layer also forms a barrier to prevent the solder bumps from reacting with the underlying electrodes. In addition to the adherence layer, the pads can include a solder wettable layer, such as copper, or other metal having a solderable metallurgy.
Typically, the pads are formed by evaporating, chemical vapor depositing, or electrodepositing the different metal layers through the openings in the passivation layer and onto the electrodes. Following deposition, the solder bumps can be reflowed at about 350xc2x0 F. to melt and homogenize the bumps. The reflow process also forms the bumps into a hemispherical shape.
Metal masks, or stencils, are typically utilized for depositing the adherence and solder wettable layers onto the electrodes, and for depositing the solder bumps onto the solder wettable pads. Sometimes different masks are employed for each deposition step. For a wafer level bump fabrication process, the masks must be aligned and secured to the wafer each time using tooling fixtures. In general, aligning and securing the masks to the wafers is a time consuming and labor intensive process. It would be advantageous to perform the bump fabrication process without masks.
In addition, the wafer is often subjected to high temperatures during the bump fabrication process and during reflow of the solder bumps. With most semiconductor components it is desirable to maintain a low thermal budget during manufacture, to prevent degradation of semiconductor devices contained on the component. Accordingly, low temperature bump fabrication processes would be advantageous in fabricating bumped semiconductor components.
Still further, vacuum deposition processes, such as evaporation, CVD and electrodeposition, require fabrication equipment used by manufacturers for other semiconductor fabrication processes. However, some metals utilized in fabricating solder bumps, particularly copper, can be contaminants to other fabrication processes. Accordingly, it would be advantageous to perform the bump fabrication process without subjecting other semiconductor fabrication processes to contaminants.
In view of the foregoing, the present invention is directed to an improved method and system for fabricating solder bumps for semiconductor components.
In accordance with the present invention, an improved method and system for fabricating solder bumps for bumped semiconductor components are provided. The method includes the steps of: cleaning and activating electrodes of a semiconductor component for subsequent electroless deposition; electrolessly depositing adherence layers and solder wettable layers on the cleaned and activated electrodes; and then depositing solder bumps on the electrolessly deposited layers using a wave soldering process.
In an illustrative embodiment, the method is performed on a semiconductor wafer having aluminum electrodes embedded in a glass passivation layer. The method can also be used to fabricate solder bumps on semiconductor dice, chip scale packages, and ball grid array substrates.
During formation of the electrolessly deposited layers, temperatures of less than 100xc2x0 C. are employed. In addition, each successive layer is formed on an exposed underlying layer, such that masks are not required to locate the underlying layers, or the solder bumps. Preferred materials for the adherence layers include nickel, zinc, chromium, and palladium. Preferred materials for the solder wettable layers include palladium and gold. A size and topography of the solder bumps can be controlled during the wave solder deposition process, such that a solder reflow is not required.
An illustrative system for performing the method comprises: a cleaning and activating bath containing a zincate solution for cleaning and activating the aluminum electrodes on the component; an adherence bath containing a nickel containing solution for electrolessly depositing nickel adherence layers on the aluminum electrodes; a solder wettable bath containing a palladium containing solution for electrolessly depositing palladium solder wettable layers on the adherence layers; and a wave soldering apparatus for depositing solder bumps on the solder wettable layers.